In ModelSim we have to load the delay definition file. Port(a, b : in std_logic_vector(1 downto 0) ĪEDA Simulation Tool->Run EDA Gate-Level Simulation. Signal a, b : std_logic_vector(1 downto 0) You can assert values to your design inputs with another vhdl file encapsulating it: Now you should see the simulation results in the wave panel. Now we can assert values for input signals. You can add other signals by drag and drop it in the wave panel. Now select the desired signal in the Object panel, right click and choose Add to Wave->Selected Signals. Expand the work library and double-click on the entity you want to simulate. ModelSim should pop-up and you should see a Library tab in the Workspace panel on the left. Remember you can generate vhdl from a bdf by opening the bdf file and going in Files->Create / Update->Create HDL Design File for Current File.Ĭompile your project and run the ModelSim RTL Simulation by selecting Tools->EDA Simulation Tool->Run EDA RTL Simulation. If you have schematic files replace them with VHDL files. We will talk about this last option later, for now let the options unchanged and return to your project. In the options below you can choose to simulate directly the top level entity of your design or to run it from a testbench file. In the Tool names List select ModelSim-Altera. Open your tutorial project, and choose Assignments->EDA Tool Settings and select Simulation in the left panel. Using ModelSim-Altera with a Quartus Project Enter the installation path for ModelSim-Altera. In the Option dialog window go in General / EDA Tool Options. To be able to run ModelSim, Quartus needs to know it's path. 2.2 Simulation input vector with a testbench.2.1 Simulation input vector with a script.2 Using ModelSim-Altera with a Quartus Project.
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